1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a nonvolatile memory device.
2. Description of the Related Art
Nonvolatile memory devices retain data even when an external power source is removed.
Nonvolatile memory devices can generally be categorized as MASK ROM, an EPROM, and an EEPROM.
FIGS. 1A, 1B and 1C are a plan view of a general EEPROM, a cross-sectional view taken along line I-I′ of FIG. 1A, and an equivalent circuit thereof, respectively. Referring to FIGS. 1A, 1B and 1C, a source region 12s, a drain region 12d, and a floating diffusion region 12f are provided in an active region 12 defined by device isolation layers 13 in a semiconductor substrate 11.
A word line WL is provided across the active region 12, extending in a first direction. A select line SL is spaced apart from the word line WL parallel thereto, and is likewise provided across the active region. A bit line BL is connected to the source region 12s through a bit line contact plug 31, and extends in a second direction transverse to the first direction.
A floating gate electrode 21, an intergate dielectric layer 23, and a control gate electrode 25 are stacked on an active region between the source region 12s and the floating diffusion region 12f, and a gate insulating layer 15 is interposed between the floating gate electrode and the active region. The control gate electrode 25 is connected to the word line WL. The floating diffusion region 12f extends into the active region under the word line WL. A memory transistor MT of the device can include the source region 12s, the floating diffusion region 12f, and a stacked gate electrode including the floating gate electrode 21, the intergate dielectric layer 23 and the control gate electrode 25. A portion of the gate insulating layer 15 may have an opening that exposes the active region, and a tunnel insulating layer (not shown) that is thinner than the gate insulating layer can be provided at the opening.
A select gate electrode 27 is provided on an active region between the floating diffusion region 12f and the drain region 12d, and a select gate insulating layer 17 is interposed between the select gate electrode and the active region. The select gate electrode 27 is connected to the select line SL. A select transistor ST may include the select gate electrode 27, the floating diffusion region 12f, and the drain region 12d. As compared to the memory transistor MT, the select transistor ST may have a general MOS transistor structure. However, the select transistor ST may optionally have a stacked structure, including conductive layers for the floating gate electrode and the control gate electrode. The conductive layers may be electrically connected to each other through an opening.
A memory cell unit of the conventional EEPROM described above includes one select gate and one memory gate, which can store only one-bit of data and does not lend itself toward higher integration.